Semiconductor storage devices typified by DRAM (Dynamic Random Access Memory) are widely used as the main memory of servers and other computers, but with the increase in hardware speed and software complexity, the storage capacity required in main memory continues to increase. For this reason, it is difficult to meet the storage capacity needs required in main memory by using only a single memory chip, and a module referred as DIMM (Dual Inline Memory Module) in which a plurality of memory chips are mounted on a module substrate is ordinarily used.
However, the number of memory chips that can be mounted is low and the resulting storage capacity is limited when the memory chip is disposed in a flat configuration on a module substrate. Methods have been proposed in which a plurality of memory chips are three-dimensionally stacked and packaged, and the memory chips are mounted on a module substrate. See Japanese Patent Application Laid-Open Nos. H2-290048, 2001-110978, 2001-273755, and 2004-327474.
FIG. 22 is a schematic diagram of a conventional semiconductor storage device that is three-dimensionally stacked and packaged. The semiconductor storage device shown in FIG. 22 has a structure in which two memory chips 10 and 11 are stacked on the base substrate 20, and the base substrate 20 is mounted on a module substrate (not shown). Each of the memory chips 10 and 11 has a memory array MA, a command/address pad CAP to which commands and addresses are supplied, a chip select signal pad CSP to which a chip select signal is supplied, a data input/output pad DQP for inputting and outputting data, and a power pad VSP for supplying power.
The command/address pad CAP, data input/output pad DQP, and power pad VSP each have a shared connection with the memory chip 10 and memory chip 11, and are brought together in the command/address external terminal group CA, data input/output external terminal group DQ, and power supply external terminal group VS, respectively, on the base substrate 20. On the contrary, the chip select signal pad CSP does not share a connection, and the chip select signal pad CSP of the memory chip 10 is connected to the chip select signal external terminal CSO, and the chip select signal pad CSP of the memory chip 11 is connected to the chip select signal external terminal CS1. The purpose of this configuration is to allow the memory chips. 10 and 11 to be selectively activated.
Another method has recently been proposed whereby the core unit in which the memory cell is formed and the interface unit in which the peripheral circuit for the memory cell is formed are each placed in a separate chip, and higher storage capacity and higher speeds are made possible by stacking these chips. This means that semiconductor storage devices that are conventionally composed of a single chip are divided into a plurality of chips. This method therefore allows the capacity of the chip (core chip) in which the core unit is formed to be increased, and makes it possible to obtain a very large storage capacity by furthermore stacking the core chips.
However, since the semiconductor storage device shown in FIG. 22 is configured so that the command/address external terminal group CA and data input/output external terminal group DQ are connected to the memory chips 10 and 11, there is a problem in that the parasitic capacitance of the command/address external terminal group CA and the data input/output external terminal group DQ is considerable in comparison with ordinary semiconductor storage devices in which only a single chip has been packaged.
Since such parasitic capacitance is the cause of signal waveform disturbance, there is a possibility that an adequate operating margin cannot be assured when the interface speed is very high, that is, when the clock speed exceeds 1 GHz, for example. This problem makes it difficult to make the capacity sufficiently large by using the method shown in FIG. 22 because the problem is made more conspicuous as the number of memory chips to be stacked increases.
Also, since the semiconductor storage device shown in FIG. 22 is different from an ordinary semiconductor storage device in which only a single chip has been packaged in the sense that two chip select signal external terminals are provided (CS0, CS1) compatibility with ordinary semiconductor storage devices is therefore lost. For this reason, a special-purpose memory controller must be designed in order to use the semiconductor storage device shown in FIG. 22, and the overall cost of the system is liable to increase.
Using the method described in Japanese Patent Application Laid-Open No. 2004-327474 appears to be able to solve the above-described problems, but this configuration is fundamentally different from the type of semiconductor storage device in which memory chips that are capable of independently carrying out read and write operations are stacked, and is rather a configuration in which core chips that are not capable of independently carrying out read and write operations are stacked, as shown in FIG. 22.
Therefore, an ordinary memory chip naturally cannot be used and a special-purpose chip must be newly designed. Also, with the configuration described in Japanese Patent Application Laid-Open No. 2004-327474, a through-electrode must be formed in the chips, and other advanced manufacturing techniques that are not sufficiently established must be used. It is therefore believed that manufacturing such chips at low cost under current conditions is difficult.